The present invention relates to an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit from damaging by electrostatic discharge, and more especially, to an ESD protection circuit using for mixed voltage application.
Electrostatic discharge (ESD) phenomena, which normally occur on integrated circuits (ICs) when touched by charged human body or machines, have a grown importance in electric and semiconductor industry. Due to the extreme high-energy electrical pulse caused, the electrostatic discharges could damage the integrated circuit badly. As the semiconductor technologies tend to reducing device dimension and increasing circuit integration, the potentially destructive nature of ESD became more and more apparent. To prevent the ICs form failure by unexpected damage, the ESD phenomena should be suppressed, and protection circuits are often employed against ESD in addition to antistatic coatings to protect the main circuit elements on IC chips.
In general, the ESD protection circuits for an IC chip are coupling to the contact ports, which typically refer to as pins or inputs/output pads, of the chip needed for protection. An ESD protection circuit forms a bypass of the main circuit and constructed with a trigger voltage at which a key junction enters avalanche breakdown and the bypass of protection circuit shorts to allow a great amount of current passing through and shunted to electrical ground. After the ESD protection circuit is triggered, a low impedance mode called snap-back occurs so that the bypassed current can flow through the protection circuit under a holding voltage that is much lower than the trigger voltage. The power dissipation is thus lessened and the main circuit is prevented from experience of ESD current.
An important conventional ESD protection circuit is MOS transistor. Under ESD stress condition, a MOS transistor is desired to behave as a bipolar transistor and act as a switch. FIG. 1A shows a cross-sectional view of a typical NMOS transistor used for ESD protection circuit including source region 20 and drain region 30 in the substrate 10, and gate 40 and gate oxide 50 on the substrate. FIG. 1B shows the I-V curve of above NMOS transistor with gate 40, source 20, and substrate 10 grounded. As the drain voltage is raised positive with respect to the substrate at a normal operation mode, no current flows through the transistor. It""s because the junction 35 between the N-type doped drain 30 and P-type substrate 10 is reverse biased. The transistor is now considered to be xe2x80x9coffxe2x80x9d. When the drain bias is raised positively beyond a breakdown voltage denoted as Vb in FIG. 1B, the junction 35 enters avalanche breakdown and a large number of electron-hole pairs are generated. As the current increased, a forward bias is contributed to the junction 25 between the P-type substrate 10 and the N-type source 20, and electrons are emitted from the source 20 into the substrate. This results in constructive feedback and allows a great current passes through the transistor. The source 20 and drain 30 act as bipolar emitter and collector respectively. The NMOS switch is now xe2x80x9conxe2x80x9d at a trigger voltage denoted as Vt in FIG. 1B. A snapback effect is then occurs. The drain voltage is decreases and a negative resistance region is observed due to the availability of more carriers for multiplication until a holding level, which is denoted as Vh in FIG. 1B, is reached. Thereafter the I-V curve shows a positive resistance. In such a mechanism described above, the ESD current can be bypassed through the ESD protection device at the lower holding voltage when the instant voltage exceeds the trigger voltage. The components of the main circuit can be prevented from damage.
Above conventional NMOS transistor devices used for ESD protection encounter a problem about the mixed voltage application. As known in the art, integrated circuits, as well as computer systems were designed historically to operate under five-volt power supply. As the electric and semiconductor fabrication technology progresses, and the application market develops, lower power consumption and higher device performance are required. Lower voltage standards were then introduced. A 3.3-volt system is employed.
The new lower voltage standard were not immediately fully adopted for all applications. Devices having new standard power supply are frequently used together with those having old standard power supply. Sometimes it is needed to make new, low-voltage devices interconnected to old, high-voltage devices. For such a mixed voltage system, it must be ensured that the circuit designed to operate at lower voltage standard would not be harmed when used in the high voltage application. However, in this case, the conventional ESD protection circuit manufactured for protecting the low-voltage main device would face a high standard voltage across the thin gate oxide of the MOS transistor. Since the transistor is employed for the low-voltage protection and generally fabricated simultaneously as the protected circuit formed, the gate oxide is not designed for withstanding the high standard voltage. The high standard voltage across the gate oxide would generate strong field, increase hot carriers, and result in degradation of oxide reliability and shortening of oxide lifetime (before oxide breakdown). To do with such situation, a stack structure of NMOS transistor is developed.
Warren R. Anderson and David B. Krakauer propose a stacked structure of two NMOS transistor in a cascode configuration for mixed voltage application. In their paper xe2x80x9cESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascode Configurationxe2x80x9d in EOS/ESD SYMPOSIUM 98, p. 54-62, the mechanism is described. FIGS. 2A and 2B show a configuration of an NMOS transistor stack. In this configuration, the two transistors 210 and 230 are merged into the same active area and share a same doped region 220 as the source of the first transistor 210 and the drain of the second transistor 230. The drain 212 and gate 214 of the first transistor 210 are respectively connected to the I/O pad and the low supply voltage (Vdd). The source 232 and gate 234 of the second transistor 230 are ground. When a high supply voltage of 5 Volts appears at the pad, the voltage of the floating shared region 220 is limited to the low supply voltage minus the threshold voltage of the first transistor 210. In such voltage distribution, none of the voltage between the gate-source, gate-drain, and source-drain terminals of either transistor exceeds 3.3 volts. No dielectric and hot carrier reliability is challenged.
Warren R. Anderson and David B. Krakauer further propose a protection circuit using two sets of NMOS stack to protect the main circuit form ESD effect. As shown in FIG. 3 and in their FIG. 15, a large primary NMOS stack and a small secondary NMOS stack are coupled between the main circuit and the I/O pad with a resistor of about 100 ohms interposed. With their proposed configuration, the main circuit can be effectively protected over 2 kV ESD under human body model (HBM). However, their proposal provides NMOS stack with different configuration from the normal ones adopted in the main circuit because the normal devices in advanced semiconductor design rule are not good enough for ESD performance. Extra process for silicide block or ion implantation is necessary as they suggest.
The present invention proposes a novel electrostatic discharge (ESD) protection circuit used for mixed voltage application for protecting a mixed voltage integrated circuit against damage from electrostatic discharge. The present ESD protection circuit comprises a primary ESD device and a MOS transistor stack respectively couple to a input/output pad of the mixed voltage integrated circuit. The primary ESD device will enter a snapback mode when its terminal voltage is raised beyond a trigger voltage. The MOS transistor stack is formed in a cascode configuration comprising a first MOS transistor and a second MOS transistor form in different active areas. The first MOS transistor comprises a first gate region, a first source region and a first drain region with the first drain region coupling to the input/output pad and the first gate region coupling to a low power supply. The second MOS transistor comprises a second gate region, a second source region and a second drain region, with the second drain region coupling to the first source region, the second gate region and the second source region grounded.
The primary ESD device is selected with a junction breakdown voltage no more than the lowest junction breakdown voltage of the MOS transistor stack. Therefore the primary ESD device enters snapback prior to the MOS transistor stack.